1. Field of the Invention
The present invention relates to the forming of a MOS transistor. It more specifically relates to the forming of the gate insulator of a MOS transistor.
2. Discussion of Prior Art
In conventional MOS transistors, above the channel region, a silicon oxide insulating layer (gate insulator) forms an interface between the semiconductor substrate and the gate. The tendency of transistors to miniaturize and to have increasing operating speeds has resulted in strongly decreasing the thickness of this silicon oxide layer. As a result, leakage currents between the gate and the substrate increase. Below a given silicon oxide thickness, for example, on the order of 2 nm, the leakage currents crossing the gate insulator are no longer acceptable for current applications.
It has been suggested to form the gate insulator with a material of greater dielectric constant than silicon oxide. This enables forming a thicker gate insulator, and thus decreasing leakage currents, without modifying the gate-substrate capacitance value. It has especially been suggested to form the gate insulator with silicon oxynitride (SiON), which has a dielectric constant ranging from approximately 6 to 8, while silicon oxide has a 3.9 dielectric constant.
FIGS. 1A to 1E are partial simplified cross-section views showing steps of a method for forming a MOS transistor inside and on top of a semiconductor substrate 11, for example, made of silicon, wherein the gate insulator is made of silicon oxynitride.
FIG. 1A illustrates the forming of a silicon oxide layer 12, coating substrate 11 above the transistor channel region. Layer 12 may be formed by oxidation in a step of cleaning of the transistor channel surface in the presence of water.
FIG. 1B illustrates a rapid thermal anneal step, during which the substrate is heated up to a temperature approximately ranging from 800 to 1,200° C. in the presence of oxygen, for a short period, for example approximately ranging from a few seconds to a few minutes. During this step, oxide layer 12 transforms into a thermal silicon oxide layer 13, of better electric quality than oxide 12. Such an anneal is generally designated as RTO in the art, for “Rapid Thermal Oxidation”.
FIG. 1C illustrates a step during which nitrogen atoms are incorporated into silicon oxide layer 13. Layer 13 is exposed to a plasma comprising nitrogen, at low temperature, for example on the order of 100° C. or less. The adsorption of nitrogen atoms followed by their diffusion into the silicon oxide transforms layer 13 into a silicon oxynitride layer 14, of greater dielectric constant. Such a method is currently called DPN in the art, for “Decoupled Plasma Nitridation”.
FIG. 1D illustrates a step of thermal anneal for stabilizing the nitrogen atom concentration in layer 14. Indeed, after the nitridation, a relatively fast nitrogen desorption occurs. To stop such a desorption, the substrate is heated up for a short period, for example, approximately ranging from a few seconds to a few minutes, to a temperature approximately ranging from 800 to 1,200° C., in an atmosphere containing oxygen. This results in a slight oxidation of the surface of layer 14, which blocks the desorption and enables the stabilization of the nitrogen concentration in layer 14. An oxidation can also be observed at the interface between layer 14 and substrate 11. Such an anneal is generally called PNA in the art, for “Post-Nitridation Anneal”.
FIG. 1E illustrates the forming, after the stabilization anneal, of a conductive gate 15 coating gate insulator 14. Gate 15 is for example made of polysilicon, metal, or a stack of various conductive materials.
A disadvantage of this type of transistor is that the dielectric constant of silicon oxynitride remains relatively low and thus does not enable to satisfy the needs of the most advanced technological processes. It has been provided to form the gate insulator in materials of higher dielectric constant than silicon oxynitride, for example, materials having a dielectric constant approximately ranging from 10 to 80. Such materials are currently called “high-K” in the art. They for example comprise hafnium silicate (HfxSiyOz), hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), etc.
FIG. 2 is a partial simplified cross-section view of a MOS transistor 20 formed inside and on top of a semiconductor substrate 21, for example, made of silicon, in which the gate insulator comprises a layer 23 of hafnium silicate (HfxSiyOz). The gate oxide of transistor 20 further comprises a thin silicon oxynitride layer 22, which forms the interface between substrate 21 and layer 23. A conductive gate 25, for example, made of metal, polysilicon, or a stack of various conductive materials, coats layer 23.
Interface layer 22 is necessary to guarantee a good interface quality between the gate insulator and substrate 21. However, the presence of this layer results in decreasing the equivalent dielectric constant of the assembly formed by the stacking of layers 22 and 23. Layer 22 is thus desired to be as thin as possible.
A disadvantage of usual manufacturing processes is that they do not enable the forming of a silicon oxynitride interface layer below a given thickness (for example, on the order of 1.2 nm).